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Preliminary Technical Data
Table 19. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
ADE7566/ADE7569
Bit No.
7 to 0
Mnemonic
SCRATCH1
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 20. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit No.
7 to 0
Mnemonic
SCRATCH2
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 21. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit No.
7 to 0
Mnemonic
SCRATCH3
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 22. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit No.
7 to 0
Mnemonic
SCRATCH4
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 23. Power Control SFR (POWCON, 0xC5)
Bit No.
7
6
Mnemonic
RESERVED
METER_OFF
Default
0
0
Description
Reserved.
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
5
4
3
2 to 0
RESERVED
COREOFF
RESERVED
CD[2:0]
0
0
0
010
Reserved.
Set this bit to shut down the core if in the PSM1 operating mode.
Reserved.
Controls the core clock frequency, f CORE . f CORE = 4.096 MHz/2 CD .
CD[2:0] Result ( f CORE in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves a double instruction sequence. Global interrupts must first be disabled to ensure that the two
instructions occur consecutively. The Key SFR (KYREG, 0xC1) is set to 0xA7 and is immediately followed by a write to the POWCON SFR.
For example:
CLR EA
MOV KYREG,#0A7h
MOV POWCON, #10H
;Disable Interrupts while configuring to WDT
;Write KYREG to 0xA7 to get write access to the POWCON SFR
;Shutdown the core
NOP
NOP
Rev. PrA | Page 25 of 136
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